Sikorski Arkadiusz vel ArakuS<p>FPGA development board in a microSD form factor<br>C0-microSD<br><a href="https://defcon.social/tags/Lattice" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Lattice</span></a> <a href="https://defcon.social/tags/ICE40UP5K" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>ICE40UP5K</span></a> FPGA<br>5280 logic cells<br>120 Kbit dual-port Block RAM<br>1 Mbit (128 KB) single-port RAM<br><a href="https://defcon.social/tags/Renesas" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Renesas</span></a> <a href="https://defcon.social/tags/AT25QL128A" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>AT25QL128A</span></a> SPI Flash<br>128 Mbit (16 MB) non-volatile memory<br>Programmable I/O pins:<br>Two on-board leds (one red and one green), for status indication.<br>Six programmable I/O pins (from the microSD interface)<br>Five additional programmable pins on test pads<br>Built-in <a href="https://defcon.social/tags/Signaloid" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Signaloid</span></a> C0 <a href="https://defcon.social/tags/RISC" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>RISC</span></a>-V processor core<br>Built-in bootloader, allowing you to load new FPGA bitstreams or RISC-V applications via the SD interface</p>