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#forgefpga

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🇺🇦 haxadecimal<p>Renesas took more than two years to revise the silicon from the sampled rev AA to production rev BB, and that's the best fix they could come up with?</p><p>This suggests to me that they didn't have their "A team" working the problem.</p><p><a href="https://mastodon.social/tags/renesas" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>renesas</span></a> <a href="https://mastodon.social/tags/forgefpga" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>forgefpga</span></a></p>
🇺🇦 haxadecimal<p>Renesas released the datasheet for production rev BB of their ForgeFPGA SLG47910. They fixed the rev AA errata of not being able to use the part at Vdd=3.3V without raising Vcore to 1.5V (normally 1.2V).</p><p>The fix is that Vdd and Vddio are now specified to a maximum of 2.75V, for use at a nominal 2.5V.</p><p>Most of the potential uses I had for a super-cheap low-demsity FPGA in a tiny 3x3mm QFN are no longer viable when I would need level shifting for 3.3V I/O.</p><p><a href="https://mastodon.social/tags/renesas" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>renesas</span></a> <a href="https://mastodon.social/tags/forgefpga" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>forgefpga</span></a><br>1/</p>
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