#apicula has reached a state where it supports enough stuff (correctly supports!) to run a little Linux!
Thanks logic destroyer ( https://github.com/splinedrive/kianRiscV/tree/uLInux-tangnano20k )
#fpga #gowin #sipeed
@yrabbit
Very exciting! But please take your time with everything, I will be happy to try it out once it's ready ️
By the way, I would be very interested in your thought process and the steps involved in implementing a new primitive like ELVDS in #apicula + #yosys + #nextpnr .
Maybe someday you could toot about this in detail?
I finally decided to get the Tang Nano 9K ️
It's an FPGA dev board based on the GW1NR-LV9 FPGA chip from Gowin. The great news: the bitstream is being reverse engineered through Project Apicula.
Excited to try the open source flow and the recent additions by @yrabbit
It has just come to my attention that the vendor IDE has a VGA example as part of it.
So I just took it and compiled #yosys->#nextpnr->#apicula
And marvel: no difference! The example uses PLL and it's the same source code! (well, except for two unimportant lines, and it's not my fault - I know exactly how to code these ports, but I need to change #yosys)
#fpga