I check the firmware format with compression of both FPGA pieces and initial BSRAM content on the example of already classic two Goblins.
#fpga #gowin #apicula #sipeed

#apicula has reached a state where it supports enough stuff (correctly supports!) to run a little Linux!

Thanks logic destroyer ( https://github.com/splinedrive/kianRiscV/tree/uLInux-tangnano20k )
#fpga #gowin #sipeed

Word Search Puzzle 163

Word List : #parget #mediocre #raxing #scraplet #adam #sneap #upsit #fauns #meaw #twasome #aiawong #hamming #retiming #becrimed #callings #zupanate #topeng #apicula

http://karafinance.com/2024/02/27/word-search-puzzle-163/

#Apicula 0.10.0, #Yosys helper for #Gowin #FPGA add support for Gowin 20K based Sipeed Nano 20K and Sipeed Primer 20K. Support started in 0.8.2 with minimalist blinking.

Ladies and gentlemen, Himbaechel-#gowin supports #tangnano20k to the extent necessary for #riscv to function correctly (example attosoc). Hooray!
#apicula #sipeed #nextpnr #fpga

@yrabbit
Very exciting! But please take your time with everything, I will be happy to try it out once it's ready ️

By the way, I would be very interested in your thought process and the steps involved in implementing a new primitive like ELVDS in #apicula + #yosys + #nextpnr .
Maybe someday you could toot about this in detail?

I finally decided to get the Tang Nano 9K ️

It's an FPGA dev board based on the GW1NR-LV9 FPGA chip from Gowin. The great news: the bitstream is being reverse engineered through Project Apicula.

Excited to try the open source flow and the recent additions by @yrabbit

It has just come to my attention that the vendor IDE has a VGA example as part of it.
So I just took it and compiled #yosys->#nextpnr->#apicula

And marvel: no difference! The example uses PLL and it's the same source code! (well, except for two unimportant lines, and it's not my fault - I know exactly how to code these ports, but I need to change #yosys)
#fpga