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#apicula

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YRabbit<p>GW5 family (<a href="https://mastodon.sdf.org/tags/TangPrimer25k" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>TangPrimer25k</span></a>) got support for huge LUTs in <a href="https://mastodon.sdf.org/tags/apicula" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>apicula</span></a>!🍾 </p><p><a href="https://mastodon.sdf.org/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a>#sipeed#gowin</p>
YRabbit<p>Gee! Made base generation for <a href="https://mastodon.sdf.org/tags/TangPrimer25k" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>TangPrimer25k</span></a> where this tricky IO layout is taken into account.</p><p><a href="https://mastodon.sdf.org/tags/nextpnr" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>nextpnr</span></a> already understands that despite the fact that one and the same cell for IO is set - IOT3, the blocks A and B together with their wires are placed in different cells.</p><p>It does not work naturally - I need to set the fuses in a different cell as well 🤣 <a href="https://mastodon.sdf.org/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a> <a href="https://mastodon.sdf.org/tags/apicula" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>apicula</span></a></p>
YRabbit<p>Ladies and gentlemen! The first design for the <a href="https://mastodon.sdf.org/tags/Gowin" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Gowin</span></a> GW5A chip series to fully pass the whole Yosys-&gt;Nextpnr-&gt;Apicula-&gt;working-board chain!🍾 🍾 🍾 </p><p>The design itself is nothing to write home about - just an inversion of the LED button, but words won't convey what kind of creepy stuff I encountered inside the chip!</p><p>I'm allowed to rest a little over the weekend:)<br><a href="https://mastodon.sdf.org/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a> <a href="https://mastodon.sdf.org/tags/sipeed" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>sipeed</span></a> <a href="https://mastodon.sdf.org/tags/gowin" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>gowin</span></a> <a href="https://mastodon.sdf.org/tags/apicula" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>apicula</span></a></p>
YRabbit<p>M.2 USB SSD wakes up using <a href="https://mastodon.sdf.org/tags/ZFS" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ZFS</span></a> and <a href="https://mastodon.sdf.org/tags/FreeBSD" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FreeBSD</span></a>. I'll leave that question for later (although I have SATA mechanical drives and it would be annoying to see wake-up failures).</p><p>I need the Linux command line to create <a href="https://mastodon.sdf.org/tags/apicula" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>apicula</span></a> bases. Qemu works here, which is welcome. But 10 times slower than under <a href="https://mastodon.sdf.org/tags/DragonFlyBSD" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>DragonFlyBSD</span></a> - accel=nvmm accelerator is used there. I wonder what kind of accelerators there are under <a href="https://mastodon.sdf.org/tags/FreeBSD" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FreeBSD</span></a>?🤔</p>
YRabbit<p>@splinedrive 's <a href="https://mastodon.sdf.org/tags/riscv" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>riscv</span></a> thing is running Linux on <a href="https://mastodon.sdf.org/tags/tangnano20k" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>tangnano20k</span></a> . 🤣 But that's not the news, the news is that this is the work of a new <a href="https://mastodon.sdf.org/tags/apicula" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>apicula</span></a> that will allow support for the cool GW5A series <a href="https://mastodon.sdf.org/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a>!</p>
YRabbit<p>Gee! Beat the last two chips!</p><p>This version of <a href="https://mastodon.sdf.org/tags/apicula" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>apicula</span></a> (with new bases) is able to create the whole set of workable examples from the kit! <br><a href="https://mastodon.sdf.org/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a></p>

@yrabbit
Very exciting! But please take your time with everything, I will be happy to try it out once it's ready 😃

By the way, I would be very interested in your thought process and the steps involved in implementing a new primitive like ELVDS in #apicula + #yosys + #nextpnr .
Maybe someday you could toot about this in detail?

I finally decided to get the Tang Nano 9K 😃

It's an FPGA dev board based on the GW1NR-LV9 FPGA chip from Gowin. The great news: the bitstream is being reverse engineered through Project Apicula.

Excited to try the open source flow and the recent additions by @yrabbit

#fpga#gowin#sipeed

It has just come to my attention that the vendor IDE has a VGA example as part of it.
So I just took it and compiled #yosys->#nextpnr->#apicula

And marvel: no difference! The example uses PLL and it's the same source code! (well, except for two unimportant lines, and it's not my fault - I know exactly how to code these ports, but I need to change #yosys)
#fpga