nicdex @nicdex

**st1nger** @st1nger@infosec.exchange · 3d

**5DNEWS PLAYSET** @azuresaipan@defcon.social · Jul 14 *

**5DNEWS PLAYSET** @azuresaipan@defcon.social · Jul 12

**lopta** @lopta@mastodon.social · Jul 10

**Pyrzout** @jos1264@social.skynetcloud.site · Jul 10

**Tanguy ⧓ Herrmann** @dolanor@hachyderm.io · Jul 10

**Rafael** @IPXFong@mastodon.sdf.org · Jul 8

**argv minus one** @argv_minus_one@mastodon.sdf.org · Jul 7

Jul 7

argv minus one @argv_minus_one@mastodon.sdf.org

In the 1980s, a whole lot of computer and CPU vendors introduced shiny new #RISC processors, like ARM, MIPS, POWER, and SPARC. Many of these were quite successful in the video game, workstation, and supercomputer markets.

Except Intel, whose old-fashioned x86 machines somehow ended up outperforming almost all of the RISCs.

How did that happen?

#retrocomputing

**Pyrzout** @jos1264@social.skynetcloud.site · Jul 7

**IT News** @itnewsbot@schleuss.online · Jul 7

**Risotto Bias** @risottobias@toot.risottobias.org · Jul 6

Jul 6

Risotto Bias @risottobias@toot.risottobias.org

What does the cores to RAM ratio look like if your chip:

- is risc and doesn't have aes optimizations
- has per core "ram"
- doesn't allow cores to peek at each other's caches or buses
- doesn't have branch prediction
- communication in or out of the core means a specific location in ram needs to be written to
- has dedicated interrupt affinity cores
- has dedicated privileged cores
- lacks microcode

#risc

**N-gated Hacker News** @ngate@mastodon.social · Jul 4

**Hacker News** @h4ckernews@mastodon.social · Jul 4

**Roy Charles** @roycharles@mastodon.social · Jul 1

**Blake Patterson** @blakespot@oldbytes.space · Jul 1 *

Jul 1 *

Blake Patterson @blakespot@oldbytes.space

Did you know that the 'NT' in Windows NT stood for "Nine Ten"?

The intended core platform for the OS was the then-expected Intel i910 RISC processor, which was to be the rebranded moniker for the i860 that can be found in the wild. *

It never came to be due to the i860s terrible handling of context switching -- a capability that a CPU for a multitasking, multiuser workstation OS must be able to do _very_efficiently_. The i860 wasn't.

https://www.youtube.com/watch?v=WTkFGZqVCM8&t=459s

*** EDIT: Several have pointed to sources indicating differently that NT stood for N10, which was the codename for the i860, so -- N10, N-Ten > NT.

YouTubei860 Intel took a RISC: it did not end wellBy RetroBytes

#TIL #WindowsNT #Windows

**jbz** @jbz@indieweb.social · Jun 28

**Wolfgang Stief** @stiefkind@mastodon.social · Jun 27

Jun 27

Wolfgang Stief @stiefkind@mastodon.social

»Advances in silicon and processing technologies now give us clock speeds in excess of 40 MHz and chips with 1 million transistors!«

Source: Victor K. L. Huang – High-Performance Microprocessors: The RISC Dilemma, in “IEEE Micro August 1989 #vintagecomputing #risc #techhistory

Continued thread

**derSammler** @derSammler@oldbytes.space · Jun 22

Jun 22

derSammler @derSammler@oldbytes.space

For your viewing pleasure: the mainboard from a #digital #AlphaStation 255 and the beautiful 300 MHz Alpha 21064 CPU.

#RetroComputing #DEC #RISC

**5DNEWS PLAYSET** @azuresaipan@defcon.social · Jun 21 *

**GripNews** @GripNews@mastodon.social · Jun 17

Jun 17

GripNews @GripNews@mastodon.social

開發開源 RISC-V 核心：評估超標量、亂序執行架構的能效
➤ 開源 RISC-V 核心架構的性能與效率權衡
✤ https://arxiv.org/abs/2505.24363
本研究探討了開源 RISC-V 核心在汽車和太空等領域的需求，尤其關注超標量和亂序執行架構在提升指令週期數 (IPC) 方面的作用。研究人員修改了 XuanTie C910 核心以符合 RISC-V 標準，並推出了 CVA6S+，這是對 CVA6 核心的增強版本。透過在 22 奈米製程技術上整合到 Cheshire 開源 SoC，對 C910、CVA6S+ 和 CVA6 進行了能耗、效能、面積等綜合分析。結果顯示，CVA6S+ 在面積效率方面領先，而 C910 在能效方面表現出色，挑戰了高性能核心必然導致面積和能效降低的傳統觀念。
+ 這篇研究很有意思，證明瞭開源 RISC-V 核心在性能和效率方面有很大的潛力，對於未來嵌入式系統的發展至關重要。
+ 我一直以為高性能CPU一定很耗電，這篇文章讓我重新思考了這個問題，開源RISC-V的發展方向令人期待。
#硬件架構 #RISC-V #能效 #開源

arXiv.orgRamping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order ExecutionOpen-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) through superscalar and out-of-order (OoO) execution is crucial. However, high-performance open-source RISC-V cores face adoption challenges: some (e.g. BOOM, Xiangshan) are developed in Chisel with limited support from industrial electronic design automation (EDA) tools. Others, like the XuanTie C910 core, use proprietary interfaces and protocols, including non-standard AXI protocol extensions, interrupts, and debug support. In this work, we present a modified version of the OoO C910 core to achieve full RISC-V standard compliance in its debug, interrupt, and memory interfaces. We also introduce CVA6S+, an enhanced version of the dual-issue, industry-supported open-source CVA6 core. CVA6S+ achieves 34.4% performance improvement over CVA6 core. We conduct a detailed performance, area, power, and energy analysis on the superscalar out-of-order C910, superscalar in-order CVA6S+ and vanilla, single-issue in-order CVA6, all implemented in a 22nm technology and integrated into Cheshire, an open-source modular SoC. We examine the performance and efficiency of different microarchitectures using the same ISA, SoC, and implementation with identical technology, tools, and methodologies. The area and performance rankings of CVA6, CVA6S+, and C910 follow expected trends: compared to the scalar CVA6, CVA6S+ shows an area increase of 6% and an IPC improvement of 34.4%, while C910 exhibits a 75% increase in area and a 119.5% improvement in IPC. However, efficiency analysis reveals that CVA6S+ leads in area efficiency (GOPS/mm2), while the C910 is highly competitive in energy efficiency (GOPS/W). This challenges the common belief that high performance in superscalar and out-of-order cores inherently comes at a significant cost in area and energy efficiency.

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